Array substrate, display panel and display device

ABSTRACT

The present application discloses an array substrate, a display panel and a display device. The array substrate comprises: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, each pixel unit comprising a first pixel electrode, a second pixel electrode, and at least three thin film transistors, the pixel unit further comprising: a charge-discharge element, the charge-discharge element and a third thin film transistor in the at least three thin film transistors charging and discharging the pixel unit such that the pixel unit forms a first voltage region and a second voltage region with different voltages.

The present application is the U.S. national phase entry of PCT/CN2015/080456, with an international filing date of Jun. 1, 2015, which claims the benefit of Chinese Patent Application No. 201420627934.3, filed on Oct. 27, 2014, the entire disclosure of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present application relates to the field of display technology, particularly, to an array substrate, a display panel and a display device.

BACKGROUND OF THE INVENTION

The liquid crystal display has been widely used in field such as television, mobile phone and public information display owing to its advantages of small volume, light weight, low power consumption, low driving voltage and radiation free, which is the most widely used display technology currently. For the liquid crystal display, particularly with respect to application like large-size liquid crystal televisions, the liquid crystal display is required to have a broad visual angle range.

In the conventional liquid crystal display, the perpendicular electric field between the pixel electrode and the common electrode is mainly used to drive deflection of liquid crystal molecules. In such a case, if it is viewed at a relatively large angle deviating from the direction perpendicular to the plane of the display, the problems of low contrast and color distortion may exist, i.e., the problem of narrow visual angle (hereinafter referred to as “the visual angle”) exists.

Therefore, it is proposed in the prior art various display modes to overcome the defect that the visual angle is too narrow. The various display modes include: 90° twisted nematic liquid crystal with compensation film mode, pixel electrode pattern vertical arrangement mode and plane driving mode using fringe field, etc.

Although the above display modes have been proposed successively and have been industrialized gradually, the above various display modes still have defects in actual use. The 90° twisted nematic liquid crystal with compensation film mode is limited for improvement of the visual angle, which is only applied in laptop computers and desktop monitors generally; the pixel electrode pattern vertical arrangement mode has to fabricate the pixel electrode into a complex slit structure, which influences the light utilization efficiency; the plane driving mode using fringe field requires a high process control accuracy, has a difficult manufacturing process and affects the contrast.

To sum up, the various display modes in the prior art for overcoming the defect that the visual angle of the liquid crystal display is too narrow all have corresponding defects, which cannot increase the display visual angle of the liquid crystal display effectively.

SUMMARY OF THE INVENTION

The embodiments of this disclosure provides an array substrate, a display panel and a display device, different regions of the pixel units are charged and discharged through a charge-discharge element and a plurality of thin film transistors, thereby forming a first voltage region and a second voltage region whose voltages are different from each other, and increasing the display visual angle of the liquid crsytal display.

The array substrate provided by the embodiment of this disclosure comprises: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, each pixel unit comprising a first pixel electrode, a second pixel electrode, and at least three thin film transistors, gates of a first thin film transistor and a second thin film transistor in the at least three thin film transistors being both connected to a same gate line in the plurality of gate lines, sources of the first thin film transistor and the second thin film transistor being both connected to a same data line in the plurality of data lines, a drain of the first thin film transistor being connected to the first pixel electrode, a drain of the second thin film transistor being connected to the second pixel electrode, wherein, the pixel unit further comprises: a charge-discharge element, the charge-discharge element and a third thin film transistor in the at least three thin film transistors charging and discharging the pixel unit such that the pixel unit forms a first voltage region and a second voltage region with different voltages.

According to the above array substrate provided by the embodiment of this disclosure, by adding a charge-discharge element in the pixel unit of the array substrate, different regions of the pixel unit are charged and discharged using the charge-discharge element and a plurality of thin film transistors, thereby forming a first voltage region and a second voltage region whose voltages are different from each other, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively, moreover, the fabricating process is compatible with the existing fabricating process, and the device cost is not increased.

In a possible implementing mode, in the above array substrate provided by the embodiment of this disclosure, the pixel unit may further comprise a first auxiliary electrode, the charge-discharge element is a capacitor, the at least three thin film transistors are three thin film transistors, a gate of the third thin film transistor is connected to the gate line to which the gates of the first and second thin film transistors are connected, a source of the third thin film transistor is connected to the first pixel electrode, a drain of the third thin film transistor is connected to a first terminal of the capacitor, a second terminal of the capacitor is connected to the first auxiliary electrode, and a storage capacitance is formed between the first auxiliary electrode and the second pixel electrode. In such a case, the first auxiliary electrode may be arranged in the same layer as the gate of the third thin film transistor.

In a possible implementing mode, in the above array substrate provided by the embodiment of this disclosure, the pixel unit may further comprise a second auxiliary electrode, the charge-discharge element is a diode, a gate of the third thin film transistor is connected to the gate line to which the gates of the first and second thin film transistors are connected, a source of the third thin film transistor is connected to the first pixel electrode, a drain of the third thin film transistor is connected to a first electrode of the diode, a second electrode of the diode is connected to the second auxiliary electrode, and a storage capacitance is formed between the second auxiliary electrode and the second pixel electrode. In such a case, the second auxiliary electrode may be arranged in the same layer as the gate of the third thin film transistor.

In a possible implementing mode, in the above array substrate provided by the embodiment of this disclosure, the pixel unit may further comprise a third auxiliary electrode, the charge-discharge element is a diode, a gate of the third thin film transistor is connected to the gate line to which the gates of the first and second thin film transistors are connected, a source of the third thin film transistor is connected to the first pixel electrode, a drain of the third thin film transistor is connected to a first electrode of the diode, a first capacitance is formed between a second electrode of the diode and the third auxiliary electrode, and a storage capacitance is formed between the third auxiliary electrode and the second pixel electrode. In such a case, the third auxiliary electrode may be arranged in the same layer as the gate of the third thin film transistor.

In a possible implementing mode, in the above array substrate provided by the embodiment of this disclosure, the diode is realized through a fourth thin film transistor, a gate of the fourth thin film transistor and a source of the fourth thin film transistor are electrically connected and together serve as the first electrode of the diode, a drain of the fourth thin film transistor serves as the second electrode of the diode.

The embodiment of this disclosure provides a display panel comprising an array substrate according to this disclosure.

In a possible implementing mode, in the above display panel provided by the embodiment of this disclosure, the display panel may be a liquid crystal display panel.

According to the above display panel provided by the embodiment of this disclosure, by adding a charge-discharge element in the pixel unit of the array substrate, different regions of the pixel unit are charged and discharged using the charge-discharge element and a plurality of thin film transistors, thereby forming a first voltage region and a second voltage region whose voltages are different from each other, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively, moreover, the fabricating process is compatible with the existing fabricating process, and the device cost is not increased.

The embodiment of this disclosure provides a display device comprising a display panel according to this disclosure.

In a possible implementing mode, in the above display device provided by the embodiment of this disclosure, the display device may be a liquid crystal display device.

According to the above display device provided by the embodiment of this disclosure, by adding a charge-discharge element in the pixel unit of the array substrate in the display panel, different regions of the pixel unit are charged and discharged using the charge-discharge element and a plurality of thin film transistors, thereby forming a first voltage region and a second voltage region whose voltages are different from each other, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively, moreover, the fabricating process is compatible with the existing fabricating process, and the device cost is not increased.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a structural schematic view of an array substrate provided by an embodiment of this disclosure;

FIG. 2 is a section schematic view of the structure of array substrate as shown in FIG. 1 along A-A′ line;

FIG. 3 is a section schematic view of the structure of array substrate as shown in FIG. 1 along B-B′ line;

FIG. 4 to FIG. 6 are structural schematic views of array substrates provided by other embodiments of this disclosure;

FIG. 7 is a section schematic view of the structure of array substrate as shown in FIG. 6 along C-C′ line.

DETAILED DESCRIPTION OF THE INVENTION

Next, the specific implementing modes of the array substrate, the display panel and the display device provided by the embodiments of this disclosure will be explained in detail with reference to the drawings.

The thickness of the film layers and the sizes and the shapes of the areas in the drawings do not reflect the real proportions of the respective components of the array substrate, which only aims for illustration of the contents of this disclosure schematically.

An array substrate provided by the embodiment of this disclosure comprises: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, each pixel unit comprising a first pixel electrode, a second pixel electrode, and at least three thin film transistors, gates of a first thin film transistor and a second thin film transistor in the at least three thin film transistors being both connected to a same gate line in the plurality of gate lines, sources of the first thin film transistor and the second thin film transistor being both connected to a same data line in the plurality of data lines, a drain of the first thin film transistor being connected to the first pixel electrode, a drain of the second thin film transistor being connected to the second pixel electrode, wherein, the pixel unit further comprises: a charge-discharge element, the charge-discharge element and a third thin film transistor in the at least three thin film transistors charging and discharging the pixel unit such that the pixel unit forms a first voltage region and a second voltage region with different voltages.

The first voltage region and the second voltage region may be a high voltage region and a low voltage region whose voltages are different from each other. When the first voltage region is a high voltage region, the second voltage region is a low voltage region; or when the first voltage region is a low voltage region, the second voltage region is a high voltage region.

According to the array substrate provided by the embodiment of this disclosure, by adding a charge-discharge element in the pixel unit of the array substrate, different regions of the pixel unit are charged and discharged using the charge-discharge element and a plurality of thin film transistors, thereby forming a first voltage region and a second voltage region whose voltages are different from each other, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively, moreover, the fabricating process is compatible with the existing fabricating process, and the device cost is not increased.

In different specific implementing modes, the charge-discharge element in the pixel unit may be a capacitor, and may also be a diode or combination of the two. Next the structure of the array substrate of this disclosure will be explained in combination with the specific embodiments.

Embodiment I

FIG. 1 is a structural schematic view of an array substrate provided by embodiment I of this disclosure, FIG. 2 is a section schematic view of the structure of the array substrate as shown in FIG. 1 along A-A′ line, and FIG. 3 is a section schematic view of the structure of the array substrate as shown in FIG. 1 along B-B′ line.

Referring to FIG. 1 to FIG. 3, the pixel unit comprises a first pixel electrode 41 and a second pixel electrode 42. A gate line 10 is located between the first pixel electrode 41 and the second pixel electrode 42. In addition, as shown in FIG. 1, the pixel unit may comprise a first thin film transistor to a third thin film transistor. A connecting portion 31 of a data line 30 can be connected to sources 311 of the first thin film transistor and the second thin film transistor. In addition, the gate line 10 between the first pixel electrode 41 and the second pixel electrode 42 can serve as a common gate 11 of respective thin film transistors. A drain 321 of the first thin film transistor may be electrically connected with the first pixel electrode 41 through a first via hole 361 that penetrates a passivation layer 23. A drain 322 of the second thin film transistor may be electrically connected with the second pixel electrode 42 through a second via hole 362 that penetrates the passivation layer 23.

The connection relationship of the first to the third thin film transistors is specifically: the gate 11 of the first thin film transistor is connected to the gate line 10, the source 311 is connected to the data line 30, the drain 321 is electrically connected with the first pixel electrode 41 through the first via hole 361; the gate 11 of the second thin film transistor is connected to the gate line 10, the source 311 is connected to the data line 30, the drain 322 is electrically connected with the second pixel electrode 42 through the second via hole 362; the gate 11 of the third thin film transistor is connected to the gate line 10, the source 312 is connected to the drain 321 of the first thin film transistor, the drain 323 is arranged between the passivation layer 23 and a gate insulating layer 21.

In addition, the pixel unit may further comprise a first auxiliary electrode 13 arranged between the gate insulating layer 21 and a substrate 1, thereby the capacitor constituted by the first auxiliary electrode 13 and the drain 323 of the third thin film transistor can serve as the charge-discharge element of the pixel unit.

Next, the fabricating process of the array substrate according to Embodiment I will be explained in detail with reference to FIG. 1 to FIG. 3. The steps of fabricating the array substrate according to Embodiment I comprise:

Step I, sputtering and depositing a metal layer on the substrate 1 of the array substrate, the metal layer is for example aluminum (Al), and patterning the deposited metal layer to form the gate line 10 comprising the gate 11 and the first auxiliary electrode 13;

Step II, depositing a gate insulating layer 21 using the plasma enhanced chemical vapor deposition (PEVCD) method, the material used for example is silicon nitride;

Step III, depositing a semiconductor layer, for example, depositing amorphous silicon (a-Si) using PECVD or sputtering and depositing indium gallium zinc oxide (IGZO), and patterning the deposited semiconductor layer to form an active layer 22;

Step IV, sputtering and depositing a metal layer, the metal layer is for example aluminum (Al), and patterning the deposited metal layer to form a data line 30 comprising a connecting portion 31, sources 311 of the first thin film transistor and the second thin film transistor, source 312 of the third thin film transistor, drain 321 of the first thin film transistor, the drain 322 of the second thin film transistor and drain 323 of the third thin film transistor, forming the drain 323 of the third thin film transistor into a terminal of the capacitor that serves as the charge-discharge element, and the first auxiliary electrode 13 being the other terminal of the capacitor;

Step V, depositing the passivation layer 23, for example, depositing the silicon nitride using PECVD or coating a resin layer, and forming a first via hole 361 and a second via hole 362 in the passivation layer 23 so as to expose the drain 321 of the first thin film transistor and the drain 322 of the second thin film transistor respectively; and

Step VI, sputtering a transparent metal oxide conductive material layer, for example, indium tin oxides (ITO), and patterning the transparent metal oxide conductive material layer to form a first pixel electrode 41 and a second pixel electrode 42, the first pixel electrode 41 being electrically connected with the drain 321 of the first thin film transistor through the first via hole 361, the second pixel electrode 42 being electrically connected with the drain 322 of the second thin film transistor through the second via hole 362, and a storage capacitance being formed between the first auxiliary electrode 13 and the second pixel electrode 42.

According to respective embodiments of this disclosure, metal materials such as copper (Cu), aluminum (Al), molybdemum (Mo), titanium (Ti), chromium (Cr), tungsten (W) can be used for fabricating the gate lines and the data lines, alloys of these materials can also be used for fabricating the gate lines and the data lines. In addition, the gate line may be a single layer structure, and may also be a multi-layer structure, for example, Mo\Al\Mo, Ti\Cu\Ti, Mo\Ti\Cu.

According to the respective embodiments of this disclosure, silicon nitride or silicon oxide can be used for fabricating the gate insulating layer 21. In addition, the gate insulating layer 21 may be a single layer structure and may also be a multi-layer structure, for example, silicon oxide\silicon nitride.

According to the respective embodiments of this disclosure, the active layer 22 may use amorphous silicon or oxide semiconductor; the passivation layer 23 may use inorganics (e.g. silicon nitride), and may also use organics (e.g., resin); the first pixel electrode 41 and the second pixel electrode 42 are fabricated using transparent conductive indium zinc oxide (IZO), ITO or other transparent metal oxide conductive materials.

According to the Embodiment I of this disclosure, one terminal of the capacitor that serves as the charge-discharge element is the drain 323 of the third thin film transistor, the other terminal is the first auxiliary electrode 13. The capacitor can play the function of dividing voltage for a region (e.g. the low voltage region) of the pixel unit. When this region is charged (i.e., the gate line voltage is of a high level), the capacitor has to be charged additionally, thereby reducing the voltage of this region. When the gate line voltage is of a low level, the third thin film transistor is turned off, so as not to influence the region voltage. Therefore, a high voltage region and a low voltage region whose voltages are different from each other are formed, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively.

Embodiment II

FIG. 4 is a structural schematic view of another array substrate provided by Embodiment II of this disclosure.

Referring to FIG. 4, the pixel unit comprises a first pixel electrode 41 and a second pixel electrode 42. A gate line 10 is located between the first pixel electrode 41 and the second pixel electrode 42. In addition, as shown in FIG. 4, the pixel unit may comprise a first thin film transistor to a fourth thin film transistor. A connecting portion 31 of a data line 30 may be connected to sources 311 of the first thin film transistor and the second thin film transistor. In addition, the gate line 10 between the first pixel electrode 41 and the second pixel electrode 42 may serve as a common gate 11 of the first thin film transistor to the third thin film transistor. A drain 321 of the first thin film transistor may be electrically connected with the first pixel electrode 41 through a first via hole 361 that penetrates a passivation layer 23. A drain 322 of the second thin film transistor may be electrically connected to the second thin film transistor 42 through a second via hole 362 that penetrates the passivation layer 23.

The connection relationship of the first to the third thin film transistors is specifically: the gate 11 of the first thin film transistor is connected to the gate line 10, the source 311 is connected to the data line 30, the drain 321 is electrically connected with the first pixel electrode 41 through the first via hole 361; the gate 11 of the second thin film transistor is connected to the gate line 10, the source 311 is connected to the data line 30, the drain 322 is electrically connected with the second pixel electrode 42 through the second via hole 362; the gate 11 of the third thin film transistor is connected to the gate line 10, the source 312 is connected to the drain 321 of the first thin film transistor, the drain 323 is arranged between the passivation layer 23 and a gate insulating layer 21.

The pixel unit of the array substrate according to Embodiment II may further comprise a second auxiliary electrode 14 arranged between the gate insulating layer 21 and the substrate 1, and a diode that serves as the charge-discharge element is realized by a fourth thin film transistor. A storage capacitance can be formed between the second auxiliary electrode 14 and the second pixel electrode 42. In such a case, the second auxiliary electrode 14 may be arranged in the same layer as the gate 11 of the third thin film transistor.

The pixel unit may further comprise bridging layers 43 and 44 arranged on the passivation layer 23. The bridging layer 43 enables a gate 15 and a source 325 of the fourth thin film transistor to be connected with each other to serve as a first electrode of the diode, and a drain 324 of the fourth thin film transistor serves as a second electrode of the diode. The conduction of the diode in all the embodiments of the present invention is unidirectional conduction from the first electrode to the second electrode of the diode. The bridging layer 43 can be electrically connected with the gate 15 of the fourth thin film transistor through a third via hole 363, and can be electrically connected with the source 325 of the fourth thin film transistor through a fourth via hole 364, so as to enable the gate 15 and the source 325 of the fourth thin film transistor to be connected with each other.

In addition, the bridging layer 44 can be electrically connected with the drain 324 of the fourth thin film transistor through a fifth via hole 365, and can be electrically connected with the second auxiliary electrode 14 through a sixth via hole 366, so as to enable the drain 324 of the fourth thin film transistor to be connected with the second auxiliary electrode 14.

The gate 15 of the fourth thin film transistor can be formed simultaneously with the second auxiliary electrode 14 and the gate line 10, the active layer of the fourth thin film transistor can be formed simultaneously with the active layers of the first to the third thin film transistors, and the source 325 and the drain 324 of the fourth thin film transistor can be formed simultaneously with the sources and the drains of the first to the third thin film transistors, particularly, the source 325 of the fourth thin film transistor is connected with the drain 323 of the third thin film transistor. In addition, the bridging layers 43 and 44 can be formed simultaneously with the first pixel electrode 41 and the second pixel electrode 42 and using the same material.

FIG. 5 shows a modified embodiment of the array substrate as shown in FIG. 4.

Referring to FIG. 5, the modified embodiment as shown in FIG. 5 does not comprise the bridging layer 44 that enables the drain 324 of the fourth thin film transistor to be connected with a third auxiliary electrode 16 (corresponding to the second auxiliary electrode 14 in FIG. 4). Thereby a first capacitance is formed between the drain 324 of the fourth thin film transistor and the third auxiliary electrode 16, meanwhile, a storage capacitance is formed between the third auxiliary electrode 16 and the second pixel electrode 42.

According to Embodiment II of this disclosure, the diode (which is realized through the fourth thin film transistor) that serves as the charge-discharge element and three thin film transistors (i.e., the first to the third thin film transistors) charge and discharge different regions of the pixel unit. For example, one region (e.g. a low voltage region) is charged and discharged using one thin film transistor, and this region is unidirectionally discharged using another thin film transistor and the diode, thereby forming a high voltage region and a low voltage region whose voltages are different from each other, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively.

Embodiment III

FIG. 6 is a structural schematic view of another array substrate provided by Embodiment III of this disclosure. FIG. 7 is a section schematic view of the structure of the array substrate as shown in FIG. 6 along C-C′ line. Different from the embodiments as shown in FIG. 4 and FIG. 5 in which the fourth thin film transistor is a bottom gate structure, in the embodiments as shown in FIG. 6 and FIG. 7, the fourth thin film transistor is realized as a top gate type thin film transistor.

Referring to FIG. 6 and FIG. 7, the pixel unit comprises a first pixel electrode 41 and a second pixel electrode 42. A gate line 10 is located between the first pixel electrode 41 and the second pixel electrode 42. In addition, as shown in FIG. 6, the pixel unit may comprise a first thin film transistor to a fourth thin film transistor. The connection modes of the first thin film transistor to the third thin film transistor with the first pixel electrode, the second pixel electrode, the data lines, and the gate lines are same as Embodiment I and Embodiment II, which will not be repeated here.

As shown in FIG. 7, the pixel unit of the array substrate according to Embodiment III may further comprise a second auxiliary electrode 14 arranged between the gate insulating layer 21 and the substrate 1, and a diode that serves as the charge-discharge element is realized through a fourth thin film transistor. A storage capacitance can be formed between the second auxiliary electrode 14 and the second pixel electrode 42. In such a case, the second auxiliary electrode 14 can be arranged in the same layer as the gate 11 of the third thin film transistor.

The pixel unit may further comprise a bridging layer 43 arranged on the passivation layer 23. The bridging layer 43 enables a gate 3232 and a source 17 of the fourth thin film transistor to be connected with each other to serve as a first electrode of the diode, and a drain 18 (i.e., a part of the second auxiliary electrode 14) of the fourth thin film transistor serves as a second electrode of the diode. The drain 18 and the source 17 of the fourth thin film transistor may be arranged on the substrate 1 so as to be covered by the gate insulating layer 21. The bridging layer 43 can be electrically connected with the gate 3232 of the fourth thin film transistor through a third via hole 363 that penetrates the passivation layer 23, and can be electrically connected with the source 17 of the fourth thin film transistor through a fourth via hole 364 that penetrates the passivation layer 23 and the gate insulating layer 21, so as to enable the gate 3232 and the source 17 of the fourth thin film transistor to be connected with each other.

Step I, sputtering and depositing a metal layer on the substrate 1 of the array substrate, the metal layer is for example aluminum (Al), and patterning the deposited metal layer to form the gate line 10 comprising the gate 11, the drain 18 of the fourth thin film transistor (i.e., the second auxiliary electrode 14) and the source 17 of the fourth thin film transistor, in addition, forming N+ amorphous silicon (N+a-Si) layers 25 on the drain 18 and the source 17 simultaneously therewith through gray exposure process;

Step II, depositing a gate insulating layer 21 using PEVCD, the material used is for example silicon nitride;

Step III, depositing a semiconductor layer, for example, depositing amorphous silicon (a-Si) using PECVD or sputtering and depositing indium gallium zinc oxide (IGZO), and patterning the deposited semiconductor layer to form an active layer 22; then forming a gate insulating layer 24 on the active layer 22 of the fourth thin film transistor;

Step IV, sputtering and depositing a metal layer, the metal layer is for example aluminum (Al), and patterning the deposited metal layer to form a data line 30 comprising a connecting portion 31, sources 311 of the first thin film transistor and the second thin film transistor, source 312 of the third thin film transistor, drain 321 of the first thin film transistor, the drain 322 of the second thin film transistor, drain 323 of the third thin film transistor and gate 3232 of the fourth thin film transistor, particularly, the drain 323 of the third thin film transistor being connected with the gate 3232 of the fourth thin film transistor;

Step V, depositing a passivation layer 23, for example, depositing the silicon nitride using PECVD or coating a resin layer, and forming a first via hole 361 and a second via hole 362 in the passivation layer 23 so as to expose the drain 321 of the first thin film transistor and the drain 322 of the second thin film transistor respectively, forming a third via hole 363 that penetrates the passivation layer 23 to expose the gate 3232 of the fourth thin film transistor, and forming a fourth via hole 364 that penetrates the passivation layer 23 and the gate insulating layer 21 to expose the source 17 of the fourth thin film transistor; and

Step VI, sputtering a transparent metal oxide conductive material layer, for example, indium tin oxides (ITO), and patterning the transparent metal oxide conductive material layer to form a first pixel electrode 41, a second pixel electrode 42 and a bridging layer 43, the first pixel electrode 41 being electrically connected with the drain 321 of the first thin film transistor through the first via hole 361, the second pixel electrode 42 being electrically connected with the drain 322 of the second thin film transistor through the second via hole 362, the bridging layer 43 being electrically connected with the gate 3232 and the source 17 of the fourth thin film transistor through the third via hole 363 and the fourth via hole 364 respectively, so as to enable the gate 3232 and the source 17 of the fourth thin film transistor to be connected with each other to serve as the first electrode of the diode, and the drain 18 of the fourth thin film transistor to serve as the second electrode of the diode.

According to Embodiment III of this disclosure, the diode (which is realized through the fourth thin film transistor of the top gate type) that serves as the charge-discharge element and three thin film transistors (i.e. the first to the third thin film transistors) charge and discharge different regions of the pixel unit. For example, one region (e.g. a low voltage region) is charged and discharged using one thin film transistor, and this region is discharged unidirectionally using another thin film transistor and the diode, thereby forming a high voltage region and a low voltage region whose voltages are different from each other, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively.

The array substrate of respective embodiments of this disclosure can be applied in a display panel, particularly in a liquid crystal display panel. In the display panel, by adding a charge-discharge element in the pixel unit of the array substrate, different regions of the pixel unit are charged and discharged using the charge-discharge element and a plurality of thin film transistors, thereby forming a high voltage region and a low voltage region whose voltages are different from each other, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively, moreover, the fabricating process is compatible with the existing fabricating process, and the device cost is not increased.

The display panel comprising the array substrate according to respective embodiments of this disclosure can be applied in a display device, particularly in a liquid crystal display device. In the display device, by adding a charge-discharge element in the pixel unit of the array substrate in the display panel, different regions of the pixel unit are charged and discharged using the charge-discharge element and a plurality of thin film transistors, thereby forming a first voltage region and a second voltage region whose voltages are different from each other, such that the liquid crystal molecules have a plurality of regions with different orientations, so as to realize broad visual angle display of the liquid crystal, thereby overcoming the defect that the liquid crystal display visual angle is too narrow in the prior art, and increasing the display visual angle of the liquid crystal display effectively, moreover, the fabricating process is compatible with the existing fabricating process, and the device cost is not increased.

The display device in which the array substrate according to respective embodiments of this disclosure can be applied may be any product or component with the display function such as electronic paper, an OLED panel, a mobile phone, a panel computer, a television, a display, a laptop, a digital photo frame, a navigator etc.

Apparently, the skilled person in the art can make various modifications and variations to this disclosure without departing from the spirit and scope of this disclosure. Thus, provided that these modifications and variations of this disclosure belong to the scopes of the claims of the present application and the equivalent technologies thereof, the present application also intends to cover these modifications and variations. 

1. An array substrate, comprising: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, wherein at least one of the plurality of pixel units comprises a pixel electrode, a auxiliary line and a first thin film transistor to a fourth thin film transistor, a first electrode of the first thin film transistor is configured to receive a data signal from a data line in the plurality of data lines, a first electrode of the second thin film transistor is configured to receive the data signal, a second electrode of the second thin film transistor is connected to the pixel electrode, a second electrode of the first thin film transistor is connected to a first electrode of the third thin film transistor, and a second electrode of the third thin film transistor is connected to a first electrode of the fourth thin film transistor, wherein a first capacitance is formed between a second electrode of the fourth thin film transistor and the auxiliary line, and a second capacitance is formed between the auxiliary line and the pixel electrode.
 2. The array substrate according to claim 1, wherein a gate electrode of the fourth thin film transistor and the first electrode of the fourth thin film transistor are electrically connected.
 3. The array substrate according to claim 1, wherein the at least one pixel unit comprises a second pixel electrode, and the second electrode of the first thin film transistor is connected to the second pixel electrode.
 4. The array substrate according to claim 1, wherein gate electrodes of the first thin film transistor, the second thin film transistor and the third thin film transistor are connected to a same gate line in the plurality of gate lines.
 5. The array substrate according to claim 4, wherein at least a part of the auxiliary line and the gate electrode of the third thin film transistor are arranged in a same layer.
 6. The array substrate according to claim 1, wherein at least a part of the auxiliary line is paralleled to the data line, and/or at least a part of the auxiliary line is perpendicular to the data line.
 7. The array substrate according to claim 1, wherein the first electrodes of the first thin film transistor and the second thin film transistor are connected to the data line.
 8. An array substrate, comprising: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, wherein at least one of the plurality of pixel units comprises a pixel electrode, a auxiliary line and a first thin film transistor to a fourth thin film transistor, a first electrode of the first thin film transistor is configured to receive a data signal from a data line in the plurality of data lines, a first electrode of the second thin film transistor is configured to receive the data signal, a second electrode of the second thin film transistor is connected to the pixel electrode, a second electrode of the first thin film transistor is connected to a first electrode of the third thin film transistor, and a second electrode of the third thin film transistor is connected to a first electrode of the fourth thin film transistor, wherein a first capacitance is formed between a second electrode of the fourth thin film transistor and the auxiliary line, the auxiliary line is configured to supply a voltage, and a second capacitance is formed by the voltage from the auxiliary line and the data signal from the data line.
 9. The array substrate according to claim 8, wherein a gate electrode of the fourth thin film transistor and the first electrode of the fourth thin film transistor are electrically connected.
 10. The array substrate according to claim 8, wherein the at least one pixel unit comprises a second pixel electrode, and the second electrode of the first thin film transistor is connected to the second pixel electrode.
 11. The array substrate according to claim 8, wherein gate electrodes of the first thin film transistor, the second thin film transistor and the third thin film transistor are connected to a same gate line in the plurality of gate lines.
 12. The array substrate according to claim 4, wherein at least a part of the auxiliary line and the gate electrode of the third thin film transistor are arranged in a same layer.
 13. The array substrate according to claim 8, wherein at least a part of the auxiliary line is paralleled to the data line, and/or at least a part of the auxiliary line is perpendicular to the data line.
 14. The array substrate according to claim 8, wherein the auxiliary line is overlapped with the pixel electrode in a direction perpendicular to the array substrate.
 15. The array substrate according to claim 8, wherein the first electrodes of the first thin film transistor and the second thin film transistor are connected to the data line.
 16. A display panel comprising an array substrate as claimed in claim
 1. 17. The display panel according to claim 16, wherein the display panel is a liquid crystal display panel or an OLED display panel.
 18. A display panel comprising an array substrate as claimed in claim
 8. 19. A display device comprising a display panel as claimed in claim
 16. 20. A display device comprising a display panel as claimed in claim
 18. 